1. Field of the Invention
The present invention relates to semiconductor memory devices with a column redundancy circuit and, more particularly, to a semiconductor memory device for enhancing the repair efficiency by allocating a plurality of spare column decoders to the spare column arrays by adopting a local repairing method.
2. Discussion of Related Art
FIG. 1 is a block diagram of a conventional semiconductor memory device.
As illustrated in FIG. 1, the conventional memory device includes a plurality of memory cell arrays each made of word lines and column lines; normal column cell arrays and spare column cell arrays respectively formed in the memory cell arrays; data input/output lines connected to a data bus line of each memory cell array and for inputting/outputting the normal column data and spare column data; a global normal column decoder simultaneously selecting the normal column lines of the memory cell array; a spare column decoder simultaneously selecting the spare column lines of the memory cell array; a global normal column line selecting signal output from the global normal column decoder and for simultaneously selecting the normal column lines from each memory cell array; and a global spare column line selecting signal output by the spare column decoder and for selecting the spare column lines from the spare column array.
In the conventional memory device, the global normal column line selecting signal of the global normal column decoder is commonly connected through the normal column lines of each memory cell array. The spare column line selecting signal output from each spare column decoder is commonly connected through each spare column line of the spare column array. Therefore, structuring the circuit is easy. But, its repairing efficiency is decreased. For example, when a certain error is generated in the memory cell array 0, the memory cell arrays 1 through n are all repaired. Therefore, if the total number of the errors generated in the entire memory cell array is more than that of the spare column lines of each memory cell array, its repair is impossible and its repairing efficiency is also decreased.
FIG. 2 is a controlling circuit diagram of a memory cell array of the semiconductor memory device of FIG. 1.
As illustrated in FIG. 2, if the global normal column line selecting signal is applied to the gates of the first and second NMOS type transistors MN1 and MN2 at the state where power voltage Vcc enables the data bus line through the transistor turned on by the data bus bias signal, data of each memory cell array connected to the corresponding normal column line are output to the data bus line. Here, only the corresponding data are output through the data input/output line of each memory cell array, amplified by the data sense amplifier and output to the output port.
Meanwhile, if a certain defect is generated in the corresponding normal column line, the global normal column decoder is disabled to cut off the selection of the normal column line, and the spare column decoder outputting the spare column line selecting signal is enabled to alternate with the spare column line.
Even though the global spare column line selecting signal is applied to the gates of the third and fourth NMOS type transistors MN3 and MN4 and all data connected to the corresponding spare column lines of each spare column array are output to the data bus line, only the data connected to the data input/output line of the corresponding spare cell array are output to the output port through the data bus sense amplifier.
FIG. 3 is an operational timing diagram of FIG. 2.
As illustrated in FIG. 3, when the global normal column line selecting signal is applied at the state where the data bus bias signal is enabled to be low, the datum are outputted to the data bus line and the inverted data bus line. When the normal column line selecting signal is disabled and the global spare column line selecting signal is enabled, the normal column data are disabled and the spare column data are enabled in the data bus line and the inverted data bus line.
As described above, as the conventional column redundancy circuit uses a method for simultaneously selecting the corresponding spare column line of each spare column array through the global column decoder, the repairing efficiency of the entire defect normal column line is decreased when the number of the defected normal column lines in the entire memory cell array are more than the number of the spare column lines of each memory cell array. Moreover, other spare column lines excluding the corresponding spare column line should be repaired.